1. Field of the Invention
The present invention relates to a phase-locked loop (PLL), and more especially, to a self-test PLL and method thereof.
2. Background of the Related Art
With the development of technology, circuit design has been evolved from single chip to SOC chip. For IC of mixing signals or SOC, phase-locked loop (PLL) is essential and applied to LCD controller, video decoder, etc. It is necessary for testing to consider the difference between analog circuit and digital circuit. However, the conventional testing of PLL is executed in the way of analog test machine.
The phase-locked loop (PLL) block is a feedback control system that automatically adjusts the phase and frequency of a locally generated signal to match the phase and frequency of an input signal. FIG. 1 is a block diagram of a conventional phase-locked loop (PLL). A conventional PLL 10 receives the input signal 101(Fref) and multiplies its frequency by 103(M), for example, an integer, then outputs the output signal 102(Fout). The output signal 102 is sent to an external analog test machine 12 to measure the performance of PLL, for example, jitter, frequency, error, etc. For measuring these characteristics, a complicated testing machine is required that causes the high manufacturing cost and time consuming.